 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ir3529 page 1 of 22 february 12, 2010 data sheet xphase3 tm phase ic description the ir3529 phase ic combined with an ir xphase3 tm control ic provides a full featured and flexible w ay to implement power solutions for the latest high perfo rmance cpus and asics. the ?control? ic provides ov erall system control and interfaces with any number of ?p hase? ics which each drive and monitor a single pha se of a multiphase converter. the xphase3 tm architecture results in a power supply that is sma ller, less expensive, and easier to design while providing higher efficiency than conventional approaches. the ir3529 provides two types of current sense outp uts; ill which contains average power supply curren t, information which can be used for voltage positioni ng and ishare which contains average active phase c urrent information since current sense amplifiers of respe ctive phases are disabled when in power savings mod e. higher efficiency can be expected due to increased driver capability along with reduced non-overlap durations . turbo is included to improve load turn-on response. a shift pin now communicates to the control ic a change in phase ic on-line status resulting in controlled phase tim ing during psi and phase shedding. the ir3529 als o implements cycle-by-cycle over current protection t o resolve high repetition rate load transients. features reduced dead time 7v gate drivers (6a gatel sink current, 4a gateh s ink current) turbo mode load turn-on response enhancement programmable cycle-by-cycle over current limit pro tection phase status communicated to control ic for contro lled phase timing during psi and phase shedding power state indicator (psi) interface provides the capability to maximize the efficiency at light loa ds. anti-bias circuitry support converter output voltage up to 5.1 v (limi ted to vccl-1.8v) loss-less inductor current sensing phase delay dff bypassed during psi assertion mode to improve output ripple performance over-current protection during psi assertion mode operation feed-forward voltage mode control integrated boot-strap synchronous pfet only four external components per phase 3 wire analog bus connects control and phase ics ( vid, error amp, average power supply current) 3 wire digital bus for accurate daisy-chain phase timing control without external components debugging function isolates phase ic from the conv erter self-calibration of pwm ramp, current sense amplif ier, and current share amplifier single-wire bidirectional average current sharing small thermally enhanced 20l 4 x 4mm mlpq package rohs compliant downloaded from: http:///
ir3529 page 2 of 22 february 12, 2010 application circuit cocset shift ishare cvccl1 vout- 12v clkin phsout phsin vccl vout+ ill dacin eain psi# ccs csin- 18 csin+ 17 dacin 3 gateh 14 vccl 12 vcc 16 phsout 7 boost 13 phsin 5 pgnd 9 ill 1 eain 19 clkin 8 sw 15 gatel 10 lgnd 4 psi# 2 shift 6 ocset 11 ishare 20 ir3529 cout l rcs cbst rocset figure 1 single phase application circuit ordering information part number package order quantity IR3529MTRPBF 20 lead mlpq (4 x 4 mm body) 3000 per reel * ir3529mpbf 20 lead mlpq (4 x 4 mm body) 100 piece strips * samples only downloaded from: http:/// ir3529 page 3 of 22 february 12, 2010 absolute maximum ratings stresses beyond those listed under ?absolute maximu m ratings? may cause permanent damage to the device. these are stress ratings only and functiona l operation of the device at these or any other conditions beyond those indicated in the operationa l sections of the specifications are not implied. operating junction temperature?????.. 0 to 150 o c storage temperature range???????.-65 o c to 150 o c msl rating???????????????2 reflow temperature???????????.260 o c note: 1. maximum gateh ? sw = 8v 2. maximum boost ? gateh = 8v 3. maximum ocset = vcc 4. maximum sw ? vcc = 9v pin # pin name v max v min i source i sink 1 ill 7.5v -0.3v 1ma 1ma 2 psi# 7.5v -0.3v 1ma 1ma 3 dacin 3.3v -0.3v 1ma 1ma 4 lgnd n/a n/a n/a n/a 5 phsin 7.5v -0.3v 1ma 1ma 6 shift 7.5v -0.3v 2ma 2ma 7 phsout 7.5v -0.3v 2ma 2ma 8 clkin 7.5v -0.3v 1ma 1ma 9 pgnd 0.3v -0.3v 5a for 100ns, 200ma dc n/a 10 gatel 7.5v -0.3v dc, -5v for 100ns 5a for 100ns, 200ma dc 5a for 100ns, 200ma dc 11 ocset 25v -0.3v 1ma 1ma 12 vccl 7.5v -0.3v n/a 5a for 100ns, 200ma dc 13 boost 40v -0.3v 1a for 100ns, 100ma dc 3a for 100ns, 100ma dc 14 gateh 40v -0.3v dc, -5v for 100ns 3a for 100ns, 100ma dc 3a for 100ns, 100ma dc 15 sw 34v -0.3v dc, -5v for 100ns 3a for 100ns, 100ma dc n/a 16 vcc 25v -0.3v n/a 10ma 17 csin+ 7.5v -0.3v 1ma 1ma 18 csin- 7.5v -0.3v 1ma 1ma 19 eain 7.5v -0.3v 1ma 1ma 20 ishare 7.5v -0.3v 1ma 1ma downloaded from: http:/// ir3529 page 4 of 22 february 12, 2010 recommended operating conditions for reliable opera tion with margin 8.0v v cc 16v, 4.75v v ccl 7.5v, 0 o c t j 125 o c. 0.5v v(dacin) 1.6v, 500khz clkin 9mhz, 250khz phsin 1.5mhz. electrical characteristics the electrical characteristics involve the spread o f values guaranteed within the recommended operatin g conditions. typical values represent the median val ues, which are related to 25c. c gateh = 3.3nf, c gatel = 6.8nf (unless otherwise specified) parameter test condition min typ max unit gate drivers gateh source resistance boost ? sw = 7v. 670 m gateh sink resistance boost ? sw = 7v. 670 m gatel source resistance vccl ? pgnd = 7v. 670 m gatel sink resistance vccl ? pgnd = 7v. 300 m gateh source current boost=7v, gateh=2.5v, sw=0v. 3 a gateh sink current boost=7v, gateh=2.5v, sw=0v. 4 a gatel source current vccl=7v, gatel=2.5v, pgnd=0v. 4 a gatel sink current vccl=7v, gatel=2.5v, pgnd=0v. 6 a gatel low to gateh high delay boost = vccl = 7v, sw = pgnd = 0v, measure time from gatel falling to 1v to gateh rising to 1v 5 15 25 ns gateh low to gatel high delay boost = vccl = 7v, sw = pgnd = 0v, measure time from gateh falling to 1v to gatel rising to 1v 5 15 25 ns pwm comparator pwm ramp slope vin=12v 42 52.5 57 mv/ %dc eain bias current 0 eain 3v -25 -15 -5 a minimum pulse width note 1 55 70 ns minimum gateh turn-off time 20 80 160 ns daisy chain timing clkin bias current clkin = v(vccl) -0.5 0.0 0.5 a clkin phase delay measure time from clkin<1v to gat eh>1v 40 75 125 ns phsin pull-down resistance 30 100 170 k phsout high voltage i(phsout)=-10ma, measure vccl? phsout 1 0.6 v phsout low voltage i(phsout) = 10ma 0.4 1 v down shift pulse width 47pf load, 27% vccl 25 50 75 ns up shift pulse width 47pf load, 77% vccl 25 50 75 ns shift resistance to rails 20 50 80 k current sense amplifier csin+/- bias current i(csinm) measured with i(csinm ) sink turned off (i.e. within 8us of clkin fall and eain above body brake threshold and csinm above 75% dacin) -200 0 200 na downloaded from: http:/// ir3529 page 5 of 22 february 12, 2010 parameter test condition min typ max unit sw floating voltage measured in the application wit h the converter not switching. measure after 50us of clkin=0 with csinm shorted to sw 10 100 250 mv calibrated input offset voltage csin+ = csin- = dacin. measure input referred offset from dacin. note1 -450 +450 v gain 0.5v v(dacin) < 1.6v 31.0 32.5 34.5 v/v differential input range 0.8v v(dacin) 1.6v, note 1 -10 50 mv differential input range 0.5v v(dacin) < 0.8v, note 1 -5 50 mv common mode input range note 1 0 vccl ? 2.5v v ill rout at t j = 125 oc 3.6 4.7 5.4 k ishare rout at t j =125 oc 3.6 4.7 5.4 k current sense amplifier csin+/- bias current i(csinm) measured with i(csinm) sink turned off (i.e. within 8us of clkin fall and eain above body brake threshold and csinm above 75% dacin) -200 0 200 na sw floating voltage measured in the application wit h the converter not switching. measure after 50us of clkin=0 with csinm shorted to sw 10 100 250 mv calibrated input offset voltage csin+ = csin- = dacin. measure input referred offset from dacin. note1 -450 +450 v gain 0.5v v(dacin) < 1.6v 31.0 32.5 34.5 v/v differential input range 0.8v v(dacin) 1.6v, note 1 -10 50 mv differential input range 0.5v v(dacin) < 0.8v, note 1 -5 50 mv common mode input range note 1 0 vccl ? 2.5v v ill rout at t j = 125 o c 3.6 4.7 5.4 k ishare rout at t j =125 o c 3.6 4.7 5.4 k share adjust amplifier maximum pwm ramp floor voltage ishare = dacin ? 200mv. measure relative to floor voltage. 120 180 240 mv minimum pwm ramp floor voltage ishare = dacin + 200mv. measure relative to floor voltage. -220 -160 -100 mv body brake comparator threshold voltage with eain decreasing measure relative to floor voltage -300 -200 -110 mv threshold voltage with eain increasing measure relative to floor voltage -200 -100 -10 mv hysteresis 70 105 130 mv body brake comparator threshold voltage with eain decreasing measure relative to floor voltage -300 -200 -110 mv threshold voltage with eain increasing measure relative to floor voltage -200 -100 -10 mv hysteresis 70 105 130 mv downloaded from: http:/// ir3529 page 6 of 22 february 12, 2010 note 1: guaranteed by design, but not tested in productio n parameter test condition min typ max unit ovp comparator ovp threshold step v(ill) up until gatel drives high. compare to v(vccl) -1.0 -0.8 -0.4 v propagation delay v(vccl)=5v, step v(ill) up from v(dacin) to v(vccl). measure time to v(gatel)>4v. 15 40 70 ns synchronous rectification disable comparator threshold voltage the ratio of v(csin-) / v(dacin), below which v(gatel) is always low. 66 75 86 % over current comparator 0c, 100mv ir3529 page 8 of 22 february 12, 2010 system theory of operation system description the system consists of one control ic and a scalabl e array of phase converters, each requiring one pha se ic. the control ic communicates with the phase ics using th ree digital buses, i.e., clock, phsin, phsout and t hree analog buses, i.e., dac, ea, and iout. the digital buses a re responsible for switching frequency determinatio n and accurate phase timing control without any external component s. the analog buses are used for pwm control and cu rrent sharing between interleaved phases. the control ic incorporates all the system functions, i.e., vid, c lock signals, error amplifier, fault protections, current monitor , etc. the phase ic implements the functions requir ed by the converter of each phase, i.e., the gate drivers, pwm comparat or and latch, over-voltage protection, phase disabl e circuit, current sensing and sharing, etc. pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 1. feed-forward vo ltage mode control with trailing edge modulation is used. a high-gain and w ide-bandwidth voltage type error amplifier is imple mented in the controller?s design to achieve a fast voltage contr ol loop. input voltage is sensed by the phase ics t o provide feed- forward control. the feed-forward control compensat es the ramp slope based on the change in input volt age. the input voltage can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 psi# comparator & 8 count delay pwm comparator & latch vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 pwm comparator & latch psi# comparator & 8 count delay vid6 vid6 vid6 shift pulse generation vid6 vid6 vid6 vid6 vid6 off clk d q off vid6 vid6 vid6 vid6 + + current sense amplifier body braking share adjust amplifier 1 2 phase ic vid6 vid6 vid6 shift pulse generation vid6 vid6 vid6 vid6 shift vid6 psi ill no. of active phases monitor shift rdrp1 clkin vsetpt rcs ishare phsin dacin vcc eain gateh ccs vcch csin- csin+ gatel pgnd vccl cbst sw rthrm phsout vid6 vid6 off rcomp phsin clk d q off psi ccomp rfb + - clkin cdrp rcs + - +- ccs vout gnd rdrp vdac vo vosns+ dacin vcc ishare phsin vosns- gatel eain gateh iin vdrp lgnd fb eaout clkout csin- csin+ vin irosc vdac remote sense amplifier vid6 vcch cbst vccl gate drive voltage phsout vid6 psi rvsetpt pgnd vid6 sw vid6 + + - + thermal compensation vn vdac body braking vdrp amp ivsetpt current sense amplifier clock generator imon error amplifier share adjust amplifier rfb1 control ic cout psi# cfb1 1 2 phase ic phsout vid6 shift shift ill figure 1: pwm block diagram downloaded from: http:/// ir3529 page 9 of 22 february 12, 2010 frequency and phase timing control the oscillator is located in the control ic and the system clock frequency is programmable from 250 kh z to 9 mhz by an external resistor. the control ic system clock s ignal (clkout) is connected to clkin of all the pha se ics. the phase timing of the phase ics is controlled by the daisy chain loop, where the control ic phase clock output (phsout) is connected to the phase clock input (phsin) of th e first phase ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. the last phase ic is connected back to phsin of the control ic to complete the daisy chain loop. during power up, the control ic s ends out clock signals from both clkout and phsout pins and detects the feedback at phsin pin to determine the phase number and monitor any fault in the daisy cha in loop. when the psi is asserted (active low), the phases are ef fectively removed from the daisy chain loop. figure 2 shows the phase timing for a four phase converter. the switch ing frequency is set by the resistor rosc. the cloc k frequency equals the number of phase times the switching freq uency. phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 2: four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon receiving the falling edge of a clock pulse, the p wm latch is set and the pwm ramp voltage begins to increase. in ad dition, the low side driver is turned off and the h igh side driver is turned on after the non-overlap time expires (gatel < 1v). when the pwm ramp voltage exceeds the error amplifier?s output voltage, the pwm latch is reset and the inte rnal ramp capacitor is quickly discharged to the ou tput of the share adjust amplifier and remains discharged until the n ext clock pulse. this reset latch additionally turn s off the high side driver and enables the low side driver after the no n-overlap time concludes (switch node < 1v). the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go up to 100% duty cycle in response to a loa d step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the co mmon mode input range of the pwm comparator, results in 100% duty c ycle regardless of the voltage of the pwm ramp. thi s arrangement guarantees that the error amplifier is always in control and can demand 0 to 100% duty cyc le as required. it also favors response to a load step decrease, wh ich is appropriate, given that the low output to in put voltage ratio of most systems. the inductor current will increase mu ch more rapidly than decrease in response to load t ransients. this control method is designed to provide ?single cycle transient response.? the inductor current wil l change in response to load transients within a single switchi ng cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an ad ditional advantage of the architecture is that diff erences in ground or input voltage, at the phases, have no effect on operation since the pwm ramps are referenced to vda c. figure 3 depicts pwm operating waveforms under various condi tions. downloaded from: http:/// ir3529 page 10 of 22 february 12, 2010 phase ic clock pulse eain vdac pwmrmp gateh gatel steady-state operation duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vccluv, ocp, vid=11111x) figure 3: pwm operating waveforms body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; o min max slew v i i l t ) (* ? = the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node voltage is then forced to decrease until conduction of the sy nchronous rectifier?s body diode occurs. this increases the v oltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease i s now; bodydiode o min max slew v v i i l t + ? = ) (* since the voltage drop in the body diode is often c omparable to the output voltage, the inductor curre nt slew rate can be increased significantly. this patented technique is referred to as ?body braking? and is accomplish ed through the ?body braking comparator? located in the phase ic. if the error amplifier?s output voltage drops below the output voltage of the share adjust amplifier in the phase ic, this comparator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor, as show n in figure 4. the equation of the sensing network is, cs cs l l cs cs l c c sr sl r si c sr s v s v + + = + = 1 )( 1 1 )( )( downloaded from: http:/// ir3529 page 11 of 22 february 12, 2010 usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component o f the inductor current. figure 4: inductor current sensing and current sens e amplifier the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch currents. t he output voltage can be positioned to meet a load line based on real time information. except for a sense resistor in s eries with the inductor, this is the only sense method that can su pport a single cycle transient response. other meth ods provide no information during either load increase (low side s ensing) or load decrease (high side sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of freq uency variation. if the frequency of a particular unit is 10% low, t he peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier b andwidth, pwm prop delay, any added slope compensation, input vol tage, and output voltage are all additional sources of peak-to- average errors. current sense amplifier a high speed differential current sense amplifier i s located in the phase ic, as shown in figure 4. it s gain is nominally 32.5, and the 3850 ppm/oc increase in inductor dcr should be compensated in the voltage loop feedback path. the current sense amplifier can accept positive dif ferential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the dac voltage and sent to the control ic an d other phases through an on-chip 3k resistor connected to the ill pin. the output of t he current sense amplifier is summed with the dac voltage and sent to the phases through an on-ch ip 3k resistor connected to the ishare pin. the ill pins of all the phases are tied together and the voltage on the share bus represents the average current through a ll the inductors and is used by the control ic for voltage positioni ng. the ishare pins of all the phases are tied toge ther and are not connected to the control ic. the input offset of th is amplifier is calibrated to +/- 1mv in order to r educe the current sense error. the input offset voltage is the primary source of e rror for the current share loop. in order to achiev e very small input offset error and superior current sharing performan ce, the current sense amplifier continuously calibr ates itself. this calibration algorithm creates ripple on iout bus wi th a frequency of f sw /896 in a multiphase architecture. average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compared w ith the average current at the share bus. if curren t in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output c urrent; if current in a phase is larger than the av erage current, the c o l r l r cs c cs v o current sense amp csout i l v l v cs c downloaded from: http:/// ir3529 page 12 of 22 february 12, 2010 share adjust amplifier of the phase will pull up th e starting point of the pwm ramp thereby decreasing its duty cycle and output current. the current share amplifier is inte rnally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. for proper current sharing the output of current sense amplifier should not ex ceed (vccl-1.4v) under all operating condition. ir3529 theory of operation block diagram the block diagram of the ir3529 is shown in figure 5, and specific features are discussed in the follo wing sections. shift pulse generation . . . psi_sy nc# shift psi_sy nc . . . vccl 0.8v ovp comparator . + - ovp 0.15v debug comparator . vccl + - clk d q qb x33 current sense amplifier calibration csaout phsin + - share adjust amplifier . . . . . . . . . . . sw gateh . . pgnd gatel turbo vccl 0.75 dacin pwm comparator & latch . . oc . psi_sy nc negative current comparator & latch psi_sy nc# . . calibration oc phsin gatel enable . non-overlap time generator . synchronous rectification disable . . oc psi_sy nc cycle-by- cycle ocp + + csref . . . . gate l driver gate h driver . . . . . . . 100mv 200mv body braking comparator + - . . . ill eain vcc . boost lgnd pwm_reset gateh csin+ csin- gatel pgnd clkin dacin phsout sw ocset shift vccl psi# phsin vcc ishare psi_sy nc 200ua . . . . clk d q psi# comparator & 8 count delay . gateh enable . . . . . shift . figure 5: block diagram tri-state gate drivers the gate drivers are design to provide a 2a source and sink peak current (bottom gate driver can sink 4a). an adaptive non-overlap circuit monitors the voltage o n the gateh and gatel pins to prevent mosfet shoot- through current and minimizing body diode conductio n. the non-overlap latch is added to eliminate erro neous triggering caused by the switching noise. a fault c ondition is communicated to the phase ic via the co ntrol ic?s error amplifier without an additional dedicated sig nal line. the error amplifier?s output is driven lo w in response to any fault condition detected by the controller, suc h as vccl under voltage or output overload, disabli ng the phase ic and activating body braking tm . the ir3529 body braking tm comparator detects the low signal at the eain and drives the bottom gate output low. this tri-state o peration prevents negative inductor current and neg ative output voltage during power-down. downloaded from: http:/// ir3529 page 13 of 22 february 12, 2010 a synchronous rectification disable comparator is u sed to detect the converter?s csin- pin voltage, wh ich represents local converter output voltage. if the v oltage is below 75% of vdac and negative current is detected, gatel is driven low, which disables synchronous rec tification and eliminates negative current during p ower-up. the gate drivers are pulled low if the supply volta ge falls below the normal operating range. an 80k resistor is connected across the gateh/gatel and pgnd pins to p revent the gateh/gatel voltage from rising due to leakage or other causes under these conditions. pwm ramp every time the phase ic is powered up, the pwm ramp magnitude is calibrated to generate a 52.5 mv/% ra mp (vcc=12v). for example, a 15 % duty ratio will gen erate a ramp amplitude of 787.5 mv (15 x 52.5 mv) w ith 12v supply applied to vcc. feed-forward control is achieved by varying the pwm ramp proportionally wi th vcc voltage after calibration. in response to a load step-up, the error amplifier can demand 100 % duty cycle. as shown in figure 6, 100 % duty is detected by comparing the pwm latch output (pwmq) and its input clock (pwm_clk). if the pwmq i s high when the pwm_clk is asserted, the top fet turn off is initiated. the top fet is again turned on on ce the rmpout drops within 200 mv of the vdac. phin clkin eain (2 phase design) rmpout pwmq 100 % duty operation normal operation figure 6: pwm operation during normal and 100 % dut y mode. power state indicator (psi) function from a system perspective, the psi input is control led by the system and is forced low when the load c urrent is lower than a preset limit and forced high when load current is higher than the preset limit. ir3529 c an accept an active low signal on its psi input and force the dr ivers into tri-state, effectively, forcing the phas e ic into an off state. once the psi# signal is asserted, the ic wai ts for 8 phsin cycles before forcing the drivers in to tri-state. this delay is required to ensure that the ic does n ot respond to any high frequency psi# signal becaus e entering into psi mode for a very short duration do es not benefit the system efficiency. irrespective of the psi# input, the disabled phase remains connected to the ill bus which ensures accurate voltage positioning. however, on assertion of psi# signal, the disabled phase is disconnected from the ishare bus and there fore ishare will represent the actual per phase current information. downloaded from: http:/// ir3529 page 14 of 22 february 12, 2010 psi_sync psi 8 phsin delay d_pwm latch clk figure 7: psi assertion. turbo modulator the turbo functionality is included in ir3529 to im prove the transient performance of the system with reduced output capacitance. the turbo modulator consists of a comparator that monitors the eain signal and its filtered version. the modulator turns on the phase when eain reaches 260 mv above its filtered version and turn s off when eain reaches its peak value. this action helps to achieve an improved transient response with les ser output capacitors thereby reducing the overall system cost . cycle-by-cycle over current protection ir3529 incorporates the ocset function to improve t he transient response when the load repetition rate is close to the switching frequency. when a significantly hi gh load current is cycled at the switching frequenc y of the multi- phase vr, the phases that are synchronized with the load current will experience an incremental change in the duty ratio while the other phases will experience a decrease in the duty ratio from the nominal value. this in turn will lead to huge inductor currents in the phases t hat are synchronized with the load and thereby satu rating the inductor core. eventually, this will lead to an ovp condition or failure of the high-side mosfet. in ir3529, the problem due to high repetition rate of the load is addressed by high side current sensi ng and thereby providing cycle-by-cycle over current prote ction. the over current threshold is programmed wit h an external resistor (r ocset ) connected to the ocset pin with a sink current of 200 a. the ocset comparator monitors the voltage across the on-resistance (r ds, on ) of the high-side mosfet and terminates the high s ide pulse if the sensed voltage reaches the over curren t threshold. this helps to reduce the deviation at the error amplifier output thereby improving the transient re sponse. debugging mode if the csin+ pin is pulled up to vccl voltage, ir35 29 enters into debugging mode. both drivers are pul led low and iout output is disconnected from the current sh are bus, which isolates this phase ic from other ph ases. however, the phase timing from phsin to phsout does not change . emulated bootstrap diode ir3529 integrates a pfet to emulate the bootstrap d iode. if two or more top mosfets are to be driven a t higher switching frequency, an external bootstrap diode co nnected from vccl pin to boost pin may be needed. downloaded from: http:/// ir3529 page 15 of 22 february 12, 2010 after ovp fault latch 130mv output voltage (vo) ovp threshold vccl-800 mv ovp condition normal operation iout(ishare) gatel (phase ic) gateh (phase ic) vdac error amplifier output (eaout) figure 8: over-voltage protection waveforms over voltage protection (ovp) the ir3529 includes over-voltage protection that tu rns on the low side mosfet to protect the load in t he event of a shorted high-side mosfet, converter out of regula tion, or connection of the converter output to an e xcessive output voltage. as shown in figure 8, if iout pin v oltage is above v(vccl) ? 0.8v, which represents ov er-voltage condition detected by control ic, the over-voltage latch is set. gatel drives high and gateh drives lo w. the ovp circuit overrides the normal pwm operation and with in approximately 150ns will fully turn-on the low s ide mosfet, which remains in conduction until iout drop s below v(vccl) ? 0.8v when over voltage ends. the over voltage fault is latched in control ic and can only be reset by cycling the power to control ic. the e rror amplifier output (eain) is pulled down by control ic and will remain low. the lower mosfets alone can not clamp the output voltage however a scr or n-mosfet could be t riggered with the ovp output to prevent processor damage. operation at higher output voltage the proper operation of the phase ic is ensured for output voltage up to 5.1v. similarly, the minimum vcc for proper operation of the phase ic is 8 v. operating below this minimum voltage, the current sharing per formance of the phase ic is affected. downloaded from: http:/// ir3529 page 16 of 22 february 12, 2010 applications schematic vrrdy vid7 vid6 cvccl ccp1 cvdac rtcmp1 rvdac cvccl2 vid7 1 vid6 2 vid5 3 vid4 4 vid3 5 vid2 6 shift 30 vid1 7 vid0 8 enable 9 hotset 11 vdac 21 vdac_buff 19 vrrdy 31 vsetpt 20 phsin 27 phsout 26 eaout 16 fb 15 vdrp 17 imon 32 iin 29 ss/del 22 rosc 23 vccl 28 vn 18 vrhot 10 vosen- 12 clkout 25 psi# 24 vosen+ 13 vo 14 expad 33 ir3503 vout- rfb1 cfb vout+ rdrp rfb ccs1 ccp rsetpt csin- 18 csin+ 17 dacin 3 gateh 14 vccl 12 vcc 16 phsout 7 boost 13 phsin 5 pgnd 9 ill 1 eain 19 clkin 8 sw 15 gatel 10 lgnd 4 psi# 2 shift 6 ocset 11 ishare 20 ir3529 l1 cout1 rcs1 rtcmp2 cbst1 rcp css/del rocp1 +12v rtcmp3 rtherm vid2 vid3 vid0 vid1 vid5 vid4 vosen+ vrhot vosen- rhotset1 rhotset2 rosc psi# rmon1 cvccl4 ccs3 csin- 18 csin+ 17 dacin 3 gateh 14 vccl 12 vcc 16 phsout 7 boost 13 phsin 5 pgnd 9 ill 1 eain 19 clkin 8 sw 15 gatel 10 lgnd 4 psi# 2 shift 6 ocset 11 ishare 20 ir3529 l3 cmon rcs3 cbst3 rmon cvccl3 ccs2 l2 csin- 18 csin+ 17 dacin 3 gateh 14 vccl 12 vcc 16 phsout 7 boost 13 phsin 5 pgnd 9 ill 1 eain 19 clkin 8 sw 15 gatel 10 lgnd 4 psi# 2 shift 6 ocset 11 ishare 20 ir3529 rcs2 cbst2 iout enable vosen- cvccl5 ccs4 l4 csin- 18 csin+ 17 dacin 3 gateh 14 vccl 12 vcc 16 phsout 7 boost 13 phsin 5 pgnd 9 ill 1 eain 19 clkin 8 sw 15 gatel 10 lgnd 4 psi# 2 shift 6 ocset 11 ishare 20 ir3529 rcs4 cbst4 rocp2 cocp2 rocp3 cocp3 cocp4 rocp4 4.75v to 7.5v vccl cocp1 vosen+ vosen- figure 9: multi phase application circuit downloaded from: http:/// ir3529 page 17 of 22 february 12, 2010 design procedures - ir3529 inductor current sensing capacitor c cs and resistor r cs the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match the time constant of the inductor, and therefore th e voltage across the capacitor c cs represents the inductor current. if the two time c onstants are not the same, the ac component of the capacitor voltage is different fro m that of the real inductor current. the time const ant mismatch does not affect the average current sharing among t he multiple phases, but does affect the current sig nal iout as well as the output voltage during the load current transient if adaptive voltage positioning is adopte d. measure the inductance l and the inductor dc resist ance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c rl r = (1) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a capacitor in the range of 0.1uf to 1uf is needed for the bootstrap circuit. decoupling capacitors for phase ic a 0.1uf-1uf decoupling capacitor is required at the vccl pin. current share loop compensation the internal compensation of current share loop ens ures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loo p so that the interaction between the two loops is eliminated. the crossover frequency of current share loop is approximately 8 khz cycle-by-cycle over current protection cycle-by-cycle over current protection helps to imp rove the transient response at load repetition rate s closer to the switching frequency of the vr. the over current threshold is programmed with an external resistor (r ocset ) connected to the ocset pin with a sink current of 2 00 a. the ocset comparator monitors the voltage across the on-resistance (r ds, on ) of the high-side mosfet and terminates the high s ide pulse if the sensed voltage reaches the over current threshold. a capacitor (c ocset ) is used to reduce noise coupling into the ocset p in of the ic. r ocset = ( ) 200 , * _ _ on rds phase per iload where iload_per_phase is the maximum current per ph ase which you do not want to exceed. downloaded from: http:/// ir3529 page 18 of 22 february 12, 2010 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout; therefore, minimizing the noise coupled to the ic. dedicate at least one middle layer for a ground pl ane, which is then split into signal ground plane ( lgnd) and power ground plane (pgnd). separate analog bus (eain, dacin, and iout) from d igital bus (clkin, psi, phsin, and phsout) to reduce the noise coupling. connect pgnd to lgnd pins of each phase ic to the ground tab, which is tied to lgnd and pgnd planes respectively through vias. place current sense resistors and capacitors (r cs and c cs ) close to phase ic. use kelvin connection for the inductor current sense wires, but separate the two wires by ground polygon. the wire from the inductor terminal to csin- should not cross over the fast tr ansition nodes, i.e., switching nodes, gate drive o utputs, and bootstrap nodes. place the decoupling capacitors c vcc and c vccl as close as possible to vcc and vccl pins of the p hase ic respectively. place the phase ic as close as possible to the mos fets to reduce the parasitic resistance and inducta nce of the gate drive paths. place the input ceramic capacitors close to the dr ain of top mosfet and the source of bottom mosfet. use combination of different packages of ceramic capaci tors. there are two switching power loops. one loop incl udes the input capacitors, top mosfet, inductor, ou tput capacitors and the load; another loop consists of b ottom mosfet, inductor, output capacitors and the l oad. route the switching power paths using wide and shor t traces or polygons; use multiple vias for connect ions between layers. downloaded from: http:/// ir3529 page 19 of 22 february 12, 2010 pcb metal and component placement lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. lead land length should be equal to maximum part l ead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment an d ensure a fillet. center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper). four 0.3mm diameter vias shall be placed in the pa d land spaced at 1.2mm, and connected to ground to minimize the noise effect on the ic and to transfer heat to the pcb. no pcb traces should be routed nor vias placed und er any of the 4 corners of the ic package. doing so can cause the ic to rise up from the pcb resulting in poor solder joints to the ic leads. downloaded from: http:/// ir3529 page 20 of 22 february 12, 2010 solder resist the solder resist should be pulled away from the m etal lead lands and center pad by a minimum of 0.06mm. the solder resist mis-alignment is a maxim um of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). ther efore, pulling the s/r 0.06mm will always ensure nsmd pads. the minimum solder resist width is 0.13mm. at the inside corner of the solder resist where the lead l and groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lea d lands from the pad land. the 4 vias in the land pad should be tented with s older resist 0.4mm diameter, or 0.1mm larger than t he diameter of the via. downloaded from: http:/// ir3529 page 21 of 22 february 12, 2010 stencil design the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimi ze the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the s tencil apertures should not be made narrower; openi ngs in stencils < 0.25mm wide are difficult to maintain repeatable solder release. the stencil lead land apertures should therefore b e shortened in length by 80% and centered on the le ad land. the land pad aperture should be striped with 0.25m m wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. the maximum length and width of the land pad stenc il aperture should be equal to the solder resist op ening minus an annular 0.2mm pull back to decrease the in cidence of shorting the center land to the lead lan ds when the part is pushed into the solder paste. downloaded from: http:/// ir3529 page 22 of 22 february 12, 2010 package information 20l mlpq (4 x 4 mm body) ? ja = 36 o c/w, jc = 3.6 o c/w data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on ir?s web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on . downloaded from: http:/// |
Price & Availability of IR3529MTRPBF
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |